Improvement in the LDPC Error Correction Process Based on FPGA Implementation

Tarigan Aditia; Rita Purnamasari; Efa Maydhona Saputra

doi:10.25124/jmecs.v1i1.1476

Authors

Tarigan Aditia School of Electrical Engineering, Telkom University
Rita Purnamasari School of Electrical Engineering, Telkom University
Efa Maydhona Saputra School of Electrical Engineering, Telkom University

DOI:

https://doi.org/10.25124/jmecs.v1i1.1476

Keywords:

Error Correction, FPGA, LDPC, Matrix, Message passing

Abstract

LDPC is one of channel coding technique which can achieve the nearest to the shannon limit. The focus of this paper is to give improvement for LDPC error correcting process using message passing algorithm. This works used FPGA Cyclon II for implementing the process. This paper worked with two different LDPC matrix, matrix (8, 16) and matrix (24, 48). Matrix (24,48) had w_c = 4 and w_r = 8. Matrix (8, 16) had w_c = 2 and w_r = 4. The comparison of these two matrix would present the effects in the error correcting decision for message passing algorithm and the effect for implementing the algorithm on FPGA Cyclon II. This research purpose was to prove message passing algorithm can provide more than one bit error correction.